Energy Conservation in Memory Hierarchies using Power-Aware Cached-DRAM

Main memory has become one of the largest contributors to overall energy consumption and offers many opportunities for power/energy reduction. In this paper, we propose a new memory organization, called Power-Aware Cached-DRAM (PA-CDRAM), that integrates a moderately sized cache directly into a memory module. We use this cache to turn a memory bank off immediately after a memory access to reduce power consumption. While other work has used CDRAM to improve memory performance, we modify CDRAM to reduce energy consumption. In this paper, we describe our memory organization and show how to incorporate it into Rambus memory. We evaluate the approach using a cycle accurate processor and memory simulator. Our results show that PA-CDRAM achieves up to an 84% (28% on average) improvement in the energy-delay product and up to a 76% (19% on average) savings in energy alone when compared to a time-out power management technique.